The circuit detects the presence of three or more consecutive 1s in a string of bits coming through an input line.

First we have to determine what model we will use, MEALY or MOORE.

The state diagram for this type of circuit is shown in the figure.

If the input is 0, the circuit stays in S0, but if the input is 1, it goes to state S1 to indicate that a 1 was detected.

If the next input is 1, the change is to state S2 to indicate the arrival of two consecutive 1s, but if the input is 0, the state goes back to S0.

In this way, the circuit stays in S3 as long as there are three or more consecutive 1s received.

This is a Moore model sequential circuit, since the output is 1 when the circuit is in state S3 and is 0 otherwise.

For example, if the state is S0 and input is 0, then the next state is S0 and output 0.

You can try designing any other sequence detection using the same methods and verify the same using VERILOG.

Negedge Detector Verilog Code How To Control Cookies

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